Modeling and Simulation of Conducted Emission for VLSI ICs

Increasing demands on electromagnetic compatibility of electronic products especially the demands on reduced emissions of microelectronic components in combination with higher complexity of electrical circuits require development of new circuit conception techniques. Due to postulation of decreased design cycles, this can only be achieved by EMC-relevant simulations during the design phase. On the basis of the enormous complexity of digital ICs (millions of transistors on a single unit), it is essential to develop EMC/EMI models of single components, modules as well as of whole CMOSVLSI-ICs (ASICs, microcontrollers, DSPs, etc.). This article presents a modeling methodology based on a bottom-up approach which allows EMC and emission analyses of whole VLSI-ICs during the design phase.